DaqZ System and Software Description
Quantized Systems Ltd. © 2004
Stan Bleszynski (S&M Process Control Tech. Inc.)

LIST OF LIBRARY FUNCTIONS

Public member functions of class HW:

  init         - clear ports, initialize system regs and variables
  glue_rst     - reset GLUE PLD and clear ports
  usb_rst      - reset USB  PLD and clear ports
  dsp_rst      - soft reset of PLD's, DSP and re-boot from FLASH (if valid
                 programmed chip present) or from EPROM.
  adstart      - start or arm HF A/D converter
  adclksel     - set/return HF A/D clock selection
  adclk        - returns float value of HF A/D clock in kHz
  irq1sel      - set/return IRQ1  source selection
  irq2Asel     - set/return IRQ2A source selection
  adlenselw    - set/return length of HF A/D buffer in words (must be 2^n)
  adramptr     - return pointer to HF A/D RAM (32-bit data). Note: AD RAM is 
                 filled by A/D data from location adramptr+1 to adramptr+n,
                 where n=adlenselw .   Bits 12..0=AD1, 28..16=AD2, bits 12 and 28
                 are OTR (over the range) flags.
  adlensel     - set/return HF A/D buffer length selection
  adclkena     - enable/disable HF A/D clock (enable before conv., then disable)
  adtrigsel    - set/return HF A/D triggering selection
  SerialPort1InSel - set/return serial port 1 input channel selection
  lmuxtogena   - enable/disable automatic LMUX bit 0 toggle by LF A/D clock
  adclkinvert  - set/return HF A/D-2 clock invertion selection
  adrunning    - return HF A/D conversion-in-progress status
  rotpulse     - return status of ROTPULSE drive signal
  rcv_rdy      - return status flag, USB received byte and the port is ready
                 to be read by DSP.  The same purpose as IRQ0 .
                 DSP mus wait until rcv_rdy()==true before reading USB byte.
                 This flag is cleared automatically when data is read.
  send_full    - return status flag, data has been written to USB buffer and
                 is waiting to be read by host. This flag is cleared
                 automatically when the host reads data. DSP mus wait until
                 send_full()==false before writing next byte to the usb bus port. 
  USBWrite     - writes data to USB FT245 IC, error checks if data can be written by 
                 looking at /TXE flag 
  USBRead      - return the 8bits of data,no wait or status check

  BitPortU1/2  - set/read bit port U1 or U2 (test LED)

  usbirq0      - enable/disable of both IRQ0 interrupts 
  lcd_write    - pull R/nW LCD pin low and enable tri state LCD bus port (true)
  lcd_regsel   - set/clear register select (RS) pin on LCD module
  lcd_ena      - set/clear enable (E) pin on LCD module
  spare1nib    - read/write nibble from/to SPARE1 ( D[3..0] := pins 8,6,4,2 or
                 pins 5,7,9,10 := D[3..0] )
  hfmux1       - set/return channel selection of HFMUX1 for HF A/D converter 1 
  hfmux2       - set/return channel selection of HFMUX2 (the current board revision 1 & 2
                 forces the same channel number on HFMUX2 as on HFMUX1, Rev3. mods have 
                 them separated) 
  lfmux        - set/return channel selection of LFMUX for LF A/D converter  
  led          - light, dim or toggle LED (yellow or orange)
  adram_maxlen - set/return the size of 32-bit A/D RAM buffer in words.
  flash_maxlen - set/return the size of 8-bit flash memory in words	
  sysosc_kHz   - set/return freq. in kHz of ext. sys. oscillator used on the board
                 Note: DSP internal clock is 2*sysosc_kHz, setting a new sysosc
                 value causes system reset and reinitialization (but no reboot).
  lfad_type    - set/return the type of LF A/D converter used	on the board
  flashptr     - return pointer to flash memory (8-bit data)
  lfadsamprate - return the actual sampling rate of LF A/D converter (kHz),
                 or set it as close as possible (less or equal to the arg.) 
  lfad_RX_start- start LF A/D conversions (autorepeat) by enabling SPORT0A RX
  lfad_RX_end  - end LF A/D conversions by disabling SPORT0A RX
  lfad_RX_empty- return true if serial port receiver buffer is empty
                 (wait until RX is not empty before attempting to read!) 
  lfad_RX_read - read data from LFAD serial port RX buffer (no check against empty!)
  lfad_RX_rst  - reset serial port receiver, clear buffer (no setup change) 
  lfda_TX_empty- return true if serial port transmitter buffer is empty
                 (wait until TX is empty before attempting to send!) 
  lfda_TX_send - write word to LF D/A serial port buffer (must be empty!) 
  read_lfad    - wait for LF A/D serial port RX buffer to fill then read data
  write_lfda   - wait for ready then write binary code to selected D/A channel
  set_dacv     - set D/A voltage in V
  lfda_TX_rst  - reset serial port receiver, clear buffer (no setup change) 
  SPort1_RX_set  - set up SPORT1A receiver ATIP/BLER/SPARE2 (no rdiv- extern.clk & RFS)
  SPort1_RX_empty- return true if serial port receiver buffer is empty
  SPort1_RX_read - read word from SPORT1A RX buffer (must not be empty!) 
  SPort1_RX_rst  - reset serial port receiver, clear buffer (no setup change)
  SPort1_RX       - set/return SPORT1 RX ctrl & div reg. direct access (avoid it!)
  SPort1_TX       - set/return SPORT1 TX ctrl & div reg. direct access
  SPort1_TX_send  - write to SPORT1 TX data buffer and initiate transfer
  err             - error tag logger for fatal system errors.  The tags are stored
                    on LIFO stack within Comm class buffer. The function returns
                    without attempting to stop the execution nor resetting the system.
  mess            - message tag logger for warnings or info messages for Host 
  clr_errstack    - clear error stack.   Error tags are stored in LIFO stack
                    within Comm buffer and transmitted automatically. To access this 
                    stack use HW member functions poperrstack and pusherrstack.
  nerrors         - return number of errors logged in the error stack
  sdramalloc      - allocate buffer of length n in SDRAM segment specified by setup_hw 
  sdramfree       - de-allocate buffer in SDRAM
  combuflen       - set/return length of Comm data buffer in words (DSP-->Host transmission)
  combuf          - return bottom addr data buffer (DSP-->Host transmission)

    The structure of the Comm buffer is as follows:
      combuf+ErrStackLen+n+6 = checksum
      combuf+ErrStackLen+n+5 = last task output data item (#n)
      ...
      combuf+ErrStackLen+6   = first task output data item (#1)
      combuf+ErrStackLen+5   = bottom of the task output data area, see combuf_task_area
                                   (= value of n)
      combuf+ErrStackLen+4   = task selection (0=none, 1=TASK_1, etc, see combuf_tsel)
      combuf+ErrStackLen+3   = task status (see combuf_tstat))
      combuf+ErrStackLen+2   = top of error stack (old message)    
      ...
      combuf+3               = bot of err stack (new message)
      combuf+2               = number of errors logged in error stack   (nerrors)
      combuf+1               = length of the error stack in words (=ErrStackLen see SysErr.h)
      combuf                 = total Comm block length in 32-bit words (combuflen)

    Note: The total length of the combuf block must be greater or equal than the number
      of results data words including the n value itself (=n+1) plus the length of the
      error stack (=ErrStackLen=32) plus 6, that is:
                      combuflen >= ErrStackLen + n + 7
      (n is a user variable).  In case where only the error stack is being transferred
      combuflen may be set equal to ErrStackLen + 6.
     
 combuf_task_area_len - returns length (words) of task out data buffer within Comm buffer
                        (= value of n+1 from the example above) 
 combuf_task_area     - returns pointer to the task out data buffer within Comm buffer    
 combuf_tsel          - set/return task select 
 combuf_tstat         - set/return task status 
 rcvbuf               - return ptr to receive buffer
 rcvbuflen            - return length (words) of the receive buffer (const)
        
 timeoutcnt           - set/return the timeout count value (default is 0x00300000 --> 6seconds)
                        this is used by all functions that require waiting for something to 
                        happen,
                        such as USB communication, A/D conversions, RX/TX ports etc.
 timeoutcnt_1s        - timeout count giving 1s delay for a simple loop such as:
                           for( uint j=timeoutcnt_1s(); j>0 ; j-- ) asm("nop;");

 advfullscale1		- return HF A/D-1 full-scale voltage
 advfullscale2		- return HF A/D-2 full-scale voltage          
 advfullscale_set	- set-up full-scale voltages for HF A/D-1 and 2     
 lfadvref			- return/set LF A/D Vref voltage                      
 dacvref				- return/set D/A Vref voltage                   
 flash_get_id        - get FLASH memory ManufCode and DeviceCode
 flash_wr_byte       - write/program a byte to FLASH
 flash_wr_word       - write 32-bit word to FLASH, least signif. byte first
 flash_erase_all     - erase entire FLASH chip
 flash_is_sectprot   - return 1 if the sector is write-protected, 0 otherwise
 flash_rd_byte       - read byte from FLASH from the specified address
 flash_rd_word       - read 32-bit word from FLASH from the specified address, lsb first

 delay_us            - delay a specified time (in microseconds)
 min_delay_us        - return min time delay value in us, for function delay_us()
 flashboot           - write/read FLASHBOOT selector bit, to select between FLASH and EPROM
                       access.  FLASHBOOT bit is set inside boot loader kernel program
                       to boot from FLASH, and is used by FLASH read/write functions to
                       select flash chip.
 force_eprom_boot    - prevents booting from FLASH memory by writing a special data pattern
                       0x1234ABCD to address 0x00100000, then calls software reset which
                       causes the system to boot from EPROM, not FLASH.
 boardrev            - read board revision number 0..30
 syslogo             - allocate memory and set the string
 syslogo             - return ptr to the string
 sysinfo             - allocate memory and set the string
 sysinfo             - return ptr to the string
 sendbyte            - wait for TX ready and send byte through USB port
 sendword            - wait for TX ready and send word through USB port
 sendbuf             - wait for TX ready and send buffer through USB port
 sendstr             - wait for TX ready and send string through USB port
 rcvbyte             - wait for RX ready and read data buffer from USB port
 rcvword             - wait for RX ready and read data buffer from USB port
 rcvdata             - wait for RX ready and read data buffer from USB port

High level Comm CLASS MEMBER FUNCTIONS

Comm.H   - USB communication interface, higher level functions

process_cmd – process and execute user commands sent from host PC through USB
load_execute – receive binary code through USB and execute
program_flash_code – receive binary code through USB and program into boot FLASH
program_flash_data – receive binary data and program into data area of FLASH
read_flash_data – read FLASH and transmit to host PC
querry_flash – read FLASH vendor codes
erase_flash – erase FLASH
load_data – read data from host PC thru USB and load it into DSP RAM
transmit_combuf – transmit special task results data buffer from DSP to host PC through USB
setup_param – initialize DSP board parameters

  DaqZ System I/O Description

   DaqZ-1 board with ADSP-21065L ,  Memory Map:
   ------------------------------------------------
   System memmory   0x0000 0000 to 0x0007 ffff
   ------------------------------------------------
                    0x0000 0000 to 0x0000 00ff  IOP Regs
                    0x0000 0100 to 0x0000 01ff  IOP Regs of Processor ID 001
                    0x0000 0200 to 0x0000 02ff  IOP Regs of Processor ID 002
                    0x0000 0300 to 0x0000 07ff  Reserved
   Int.RAM Block 0  0x0000 8000 to 0x0000 9fff  Normal Word (32/48) Addresses
                   (0x0000 8000 to 0x0000 97ff) 48-bit words
                   (0x0000 8000 to 0x0000 9fff) 32-bit words
					  0x0000 A000 to 0x0000 Bfff  Reserved
   Int.RAM Block 1  0x0000 C000 to 0x0000 Dfff  Normal Word (32/48) Addresses
                   (0x0000 C000 to 0x0000 Cfff) 48-bit words
                   (0x0000 C000 to 0x0000 Dfff) 32-bit words
					  0x0000 E000 to 0x0000 ffff  Reserved
   Int.RAM Block 0  0x0001 0000 to 0x0001 3fff  Short Word (16) Addresses
					  0x0001 4000 to 0x0001 7fff  Reserved
   Int.RAM Block 1  0x0001 8000 to 0x0001 Bfff  Short Word (16) Addresses
					  0x0001 C000 to 0x0001 ffff  Reserved
   ------------------------------------------------
   External devices 0x0002 0000 to 0x03ff ffff

      Note:
        SDRAM  program memory can be used to store and to execute
        code directly, without overlays.
        The 48-bit program memory has a non-contiguous structure divided into 64K long segments
        Example: 
          Segment 1
            physical addresses [A23..A0] -   0x00020000 ... 0x0003ffff
            program (software) addresses -   0x00020000 ... 0x0002ffff
          Segment 0 = Segment 8 - wraps round
            physical addresses [A23..A0] -   0x00000000 ... 0x0001ffff
            program (software) addresses -   0x00000000 ... 0x0000ffff
                                                          etc
          One program address (48-bit data) is translated automatically by the 
          DSP into two consecutive physical addresses holding the total of 64-bits.
          The 48-bits of program data is mapped into the upper (MSB) portion of 
        the 64-bit physical double-word.   The lower 16 bits are zeros.
        Program memory block name (such as pm_sdram8) can be assigned to the whole
        physical 64Kw segment (but no more), or to a portion of it that is smaller
        than 64Kw.  In the later case, more than one (non-overlapping) memory blocks
        may lie within a single segment

   ------------------------------------------------
   External    MS0  0x0002 0000 to 0x0041 ffff  SDRAM 4M x 32-bit
   External    MS0  0x0042 0000 to 0x00ff ffff  reserved for future memory expansion up
                                                to 16M words

   External    MS1  0x0100 0000 to 0x01ff ffff  Reserved (unused)

   External    MS2  0x0200 0000 to 0x02ff ffff  GLUE PLD: A/D, ADRAM, BLER & ATIP
                    0x0200 0000 to 0x0200 ffff    ADRAM 64K x 32bit, RD/WR memory buffer
                                                  for HF A/D
                    0x0240 0000 to 0x0240 0003    Control commands (WR)
                    0x0240 0000 to 0x0280 0000    Status registers (RD)
                    0x02c0 0000 to 0x02ff ffff    not used

   External    MS3  0x0300 0000 to 0x03ff ffff  USB PLD: USB interface, SPARE, LCD, FLASH MEM 
                    0x0300 0000 to 0x0300 0003    USB port control registers & data port
                    0x0340 0000 to 0x0340 0003    reserved
                    0x0380 0000 to 0x0380 0003    LCD port and SPARE port
                    0x03c0 0000 to 0x03c7 ffff    FLASH 512K x 8bit
                    0x03c8 0000 to 0x03ff ffff    not used

   INTERRUPT       SOURCE        MEANING
   ---------------------------------------------------------------------------------------------
       IRQ0        USB  PLD      USB command or data byte has arrived and is ready to read by DSP
                                 (same as RCVRDY flag)
       IRQ1        GLUE PLD      A/D end of conversion or (selectable) A/D trigger or ROTPULSE
       IRQ2        ---           reserved (not used)

   MEMORY MAPPED REGISTERS

   ADDRESS       BITS    OPERATION   BIT NAME          MEANING 
   -------------------------------------------------------------------------------------------
                                         --- GLUE PLD ---
   QUAD0 
   0x0200 0000    D[31..0] WR/RD     ADRAM             Accessing 64KW SRAM containing 
    ... 0x0200 ffff                                    HF A/D samples

   QUAD1 CMD0
   0x0240 0000    D0        WR       GRST              Reset GLUE PLD (similiar to power reset)
                  D1        WR       ADSTART           Start A/D (only if ADTRIGSEL[1,0]=0)

   QUAD2 CMD1
   0x0240 0001    D[3..0]   WR       ADCLKSEL[3..0]    Select A/D clock 0=60MHz, 1=30, 2=15,
                                                       3=7.5, 4=3.75, 5=1.875, 6=0.9375,
                                                       7=0.4688MHz.  10..15=reserved
                  D[5,4]    WR       IRQ1SEL[1,0]      Select IRQ1 interrupt source: 0=disable,
                                                       1=start of A/D run, 2=end of A/D run, 
                                                       3=ROTPULSE
                  D[7,6]    WR       IRQ2ASEL[1,0]     Select IRQ2A interrupt source, 0=disable,
                                                       1=ATIPSYNC, 2=MIRR, 3=CRC_OK

   QUAD1 CMD2
   0x0240 0002    D[3..0]   WR       ADLENSEL[3..0]    Select the length of A/D run (number of
                                                       Samples): 0=2 words(32-bit), 1=4w, 
                                                       2=8w,3=16w, 4=32w, 5=64w, 6=128w, 7=256w, 
                                                       8=512w, 9=1024w, 10=2048w, 11=4096w,
                                                       12=8192w, 13=16384w, 14=32768w, 15=65536w.
                  D4        WR       ADCLKDIS          1=Disable A/D clock (power save),
                                                       0=enable (default)
                  D[6,5]    WR       ADTRIGSEL[1,0]    Select A/D triggering source/method: 
                                                       0=by ADSTART bit, 1=ROTPULSE,
                                                       2=CRC_OK pulse, 3=NOT(ROTPULSE)
                  D7        WR       ATIPNOTBLER       Select source for SPORT1 output: specfic 
                                                       to CD-R/RW application.

   QUAD1 CMD3
   0x0240 0003    D0        WR       SPORTENA          Enable SPORT1 out. signals from GLUE:
                                                       1=ena,
                                                       0=disable(to share SPORT1 thru SPARE2
                                                       expansion conn.)
                  D1        WR       LMUXTOGENA        Enable LMUX0 (LF mux) toggle by RFS0 
                                                       (LF A/D clock)
                  D2        WR       ADCLK2INV         Invert ADCLK2 (doubling the effective
                                                       sampling rate) 
                  D[7..3]   WR       ---               Reserved

   QUAD2 CMD0
   0x0280 0000    D0        RD       ADRUN             A/D status: 1=A/D converter is running,
                                                       0=ready
                  D1        RD       ROTPULSE          ROTPULSE status
                  D2        RD       CRC_OK            CRC_OK status: 1=OK, 0=error
                  D3        RD       BLERFRAME         BLER frame synchronization mark
                  D4        RD       ATIPSYNC          ATIP frame synchronization mark
                  D5        RD       ATIPCLK           ATIP clock
                  D6        RD       ATIPDATA          ATIP data 
                  D7        RD       MIRR              Mirror mark pulse

   QUAD3 
   0x02c0 0000 to 0x02ff ffff                          not used
 
                                          --- USB PLD ---
   QUAD0 CMD0
   0x0300 0000    D[7..0]   WR/RD   USBDATA[7..0]      USB data byte write/read

   QUAD0 CMD1
   0x0300 0001    D[7..0]   WR/RD    ---               Not used (was Data/Command LPT write/read) 

   QUAD0 CMD2                                          STATUS REGISTER 1 
   0x0300 0002    D0        RD       FLASHBOOT         reads back the actual status of FLASHBOOT
                  D1        RD      -RXF               USB Receiver FIFO is FULL 
                  D2        RD      -TXE               USB Transmitter FIFO is EMPTY
                  D3        RD       U1                read U1 status (LED Test1)   
                  D4        RD       U2                read U2 status (LED Test2)   
                  D5        RD       USBRST#           USBRST# signal from FTDI245BM chip                            D6        RD       ---
                  D7        RD       ---

   0x0300 0002    D0        WR       FLASHBOOT         This bit selects between 
                                                       FLASH memory (=1) or
                                                       EPROM (=0).  If set to 1 by the boot
                                                       Kernel - allows booting off the FLASH 
                                                       memory using BMS# line and standard DMA
                                                       mechanism.  This bit must be also set
                                                       before any attempt to read or write to
                                                       FLASH is made.
                  D[1..2]   WR       ---               Reserved 
                  D3        WR       U1                Set high/low open drain U1 output
                                                       (LED Test1)
                  D4        WR       U2                Set high/low open drain U2 output 
                                                       (LED Test2)
                  D[5..7]   WR       ---               Reserved 

   QUAD0 CMD3 
   0x0300 0003    D0        WR       RSTUSBPLD         1=Generate reset USB PLD pulse, 
                                                       0=no action
                  D[1..7]   WR       ---               Reserved 

                                                       STATUS REGISTER 2
   0x0300 0003    D0        RD       ---               reserved
                  D[1..5]   RD       REV0..4           Board Revision No, for example 
                                                       DaqZ Rev.3 = 3
                  D[6..7]   RD       ---               reserved

   QUAD1 CMD0    
   0x0340 0000    D[7..0]   RD/WR    ---               Reserved

   QUAD1 CMD1
   0x0340 0001    D0        WR       IRQENA            Enable IRQ0: 1=enable, 0=disable
                  D[1..3]   WR       HMUXA[0..2]       High-frequency Mux for HF A/D channel 1
                  D[4..6]   WR       HMUXB[0..2]       High-frequency Mux for HF A/D channel 2
                  D7        WR       ---               Reserved

   QUAD1 CMD2     
   0x0340 0002    D[7..0]   WR       LCD[7..0]         8-bit LCD data bus output 
                                                       (Release 3+ PCB only)

   QUAD2 CMD0
   0x0380 0000    D[3..0]   WR       ---               reserved 
                  D4        WR       ---               reserved
                  D5        WR       LCDWR             Inverse of LCD -WR/RD pin: 
                                                       1=write cycle active, 0=no write
                  D6        WR       LCDREGSEL         LCD Register Select pin
                  D7        WR       LCDENA            LCD Enable pin

   0x0380 0000    D[7..0]   RD       ---               reserved

   QUAD2 CMD1
   0x0380 0001    D[3..0]   WR       S[7..4]           Output port lines of SPARE1
                                                       connector pins 5,7,9 and 10
   0x0380 0001    D[3..0]   RD       S[3..0]           Input  port lines of SPARE1
                                                       connector pins 8,6,4 and 2

   QUAD3
   0x03c0 0000                                         FLASH (if FLASHBOOT=1) or EPROM data 
                                                       read (if FLASHBOOT=0). 
   to 0x03c7 ffff  D[7..0]  RD  FLASH or EPROM[7..0]   FLASH and EPROMs are 512K x 8bit
                                                       (29F040, 27C040 etc)
   or to
      0x03cf ffff                                      Only for 1024K x 8bit EPROM chips
                                                       Current board rev 3B supports FLASH up
                                                       to 512Kx8 and EPROMs up to 1024Kx8
                                                       (27C080, 27C8001).
   0x03c0 0000                                         FLASH R/W (if FLASHBOOT=1) or EPROM data
                                                       read (if FLASHBOOT=0). 
   to 0x03c7 ffff  D[7..0]  WR  FLASH[7..0]            Write data to FLASH memory (bit FLASHBOOT
                                                       must be 1, if it is zero then no action.

Notes on booting: since DaqZ Rev 3C a dual booting  off EPROM or FLASH is supported by switching BMS# line between those two chips (see bit FLASHBOOT in USB PLD).  Since USB PLD clears FLASHBOOT bit on power up or physical reset, the default booting would proceed off the EPROM as in previous revision.  In order to enable the system to boot off the FLASH memory the following condition must be met:
1) FLASH memory chip must be plugged in, must contain a valid bootable packed code like the one
generated normally by the VDSP linker (*.ldr) for PROM; and its first data byte at internal address=0 must be other than 0xFF.
2) EPROM chip must be also in its socket and must contain a modified boot loader kernel that checks if the first FLASH data byte is not 0xFF and sets USB PLD bit FLASHBOOT=1 if that is the case (see SDRAM_Flash_kernel.asm,65L_ldr_sdram_flash.dxe).

3) SDRAM address location 0x00100000 MUST NOT contain a special data value of 0x1234ABCD, since it would stop the boot kernel loader from executing a FLASH boot, and would make it revert to the standard EEPROM boot. This feature allows to revert to EPROM boot on corrupted or improperly programmed flash by writing 0x1234ABCD to addr 0x00100000 and issuing a software reset.

4) Board Daqz must be Rev 3+ or higher. 

5) USB PLD program must be Rev 3.5 or higher,

Summary of Software Development Structure

Target DSP type:  Analog Devices' Sharc 21065L 
     32-bit microprocessor (DSP)
     DaqZ-1 - proprietary board with ADSP21065L DSP
    Quantized Systems Ltd. (C) 2000
 Hardware description 
       DSP processor:
       ADSP21065L, single, EPROM boot mode.
    DSP clock:
       30MHz, doubled internally to 60MHz.
    External RAM:
       SDRAM - 4M  x 32bit, dynamic, two 16-bit chips clocked at 60MHz,
               connected as program & data memory (/MS0). Code may be 
               executed directly from SDRAM without overlays.  See
               DaqZ_mem.h for description of memory mapping and segmentation.
       ADRAM - 64K x 32bit (up to 256K), static, <12ns access time
       
    Non-volatile storage:
       EPROM - 512K x 8bit (up to 1M), UV erasable boot memory
       Flash - 512K x 8bit, flash memory for code or data
               (code must be copied to internal RAM or SDRAM
                prior to execution).
     
 Development system for ADSP21065L:
    Software:            Analog Devices (White Mountain Software)
                         Visual DSP++ V1.00
    Language:            C++ , in-line assembly 
    In-circuit emulator: Mountain-ICE (PC-ISA card to JTAG)

 Directory Structure:
      
          DaqZ_description.h - header with memory segment definitions and general
                                                 hardware descriptions, PLD, I/O addressing etc
                                   *.H         - header files for C/C++, Asm and Ldf 
                                   *.Cpp, *.C  - source files C/C++  
                                   *.Asm       - assembly source files
                                   *.Dpj       - DSP project description file (VDSP-specific)
                                   *.Ldf       - loader definition file (alloc memory segments)
                                   *.Mak       - automatically generated make file
                                   *.Ldr       - EPROM loader file (binary code for EPROM burner)
                                   .\debug\ (or release) <--- maps, objects & executables
                                            *.Doj       - compiled object modules
                                            *.Dxe       - DSP executable file (used by ICE)
                                            *.Map       - linker map listing (text file) 
                ..\BootLoader\release\65L_LDR_SDRAM.DXE - special loader kernel file for SDRAM
                                                          initialization
                ..\BootLoader\SDRAM_kernel.asm          - source for the special SDRAM kernel
                              065L_ldr_SDRAM.Dpj        - project file to generate SDRAM kernel
                              065L_ldr_SDRAM.Ldf        - linker definition file for SDRAM kernel 
                                                          built

 How to compile or modify the project using Visual DSP++:
    1) Define memory segmentation in *.Ldf file.
    2) Update sources
    3) Make sure that all relevant files *.H, *.C, *.Cpp, *.Asm, *.Ldf
       are included in the project tree
    4) Highlight project name (the root) in the project window, then open
       Project --> Project Options menu. Then select Tab:
         Project --> Processor (ADSP-2165L),
                 --> Type (DSP Executable - for ICE, or  Loader File - for EPROM)
                 --> Name (select file name for executable files)
         Compile --> enable "C++" and "Generate Debug Info"
         Load    --> Enable "Loader 21K" and select a special kernel file:
                       \BootLoader\release\65L_LDR_SDRAM.DXE
                       Note:
                       This kernel is a modified version of the default kernel 
                       21k\ldr\060_prom.dxe that properly initializes SDRAM registers
                       before the main code is loaded from EPROM into SDRAM.
                       The source for this kernel is SDRAM_kernel.Asm .
                       BootType --> PROM
                       Format   --> Hex (this is Intel Hex 32-bit format)
    5) Select Project menu --> Update Dependencies and
                           --> Rebuild All or Build Project

 EPROM types to use: 
    Package       : standard 32-pin dual-in-line (DIL-32), UV erasable or OTP
    Supply Voltage: 5V (will also accomodate 3V types after changing jumpers R278 and R277)   
    Word length   : 8-bits
    Capacity      : 128KBytes, 256K, 512K or 1MByte x 8 bit   
    Type ID       : 27C010, 27C020, 27C4001, 27C040 or 27C080

 How To Burn EPROM:
    Using a programmer, for example PB10 - select "FILE TYPE" = IH_AUTO (=Intel Hex Auto, 32-bit)
    Select the loader file (*.Ldr) to read.   Make sure that the loader file was generated
    by VDSP with selected Project-->Loader-->Format = Hex. 
  
 PLD's used: 
    Altera Max7000AE series, 3Volts
    type EP7128AETC-7 or -10, or EP7256AETC-7 or 10
    TSOP-II 100 pin (square flatpack).

 PLD development system:
    Software:        Altera  Max+PlusII Emax V9.5+ (free)
    Download cable:  ByteBlasterMV or compatible, printer port to JTAG 

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