DaqZ  DSP  Board  Specifications				
Stan Bleszynski,    Quantized Systems Ltd.     6-July-2004
Tel: +353-1-850064  
S&M Process Control Technology Inc.
 +1-705-6572519
________________________________________________________________________
Mechanical:
	Dimensions: 145x173mm, height <=15mm
	Mounting:  four holes dia 3mm, , at 79x135mm grid (79x130 to 79x140mm)
Power:
	Standard 4-way power connector (hard drive type)
	+12V/0.25A and +5V/0.5A
Electrical:
	Processor: 	Analog Devices “Sharc” family - ADSP21065L  KS-240
			Instruction cycle 16.7ns, up to 2 instructions can execute in parallel,
two data transfers per instructions.
	Processor clock: 60MHz internally (30MHz crystal osc)
	Memory:  
		- Internal processor RAM: program 6Kx48bit, data 8Kx32bit
		- External SDRAM  4Mx32bit, 16ns, for program and data 
		- A/D RAM buffer, 64Kx32bit, 16ns
		- Flash 512Kx8bit for data, 120ns (29F040, 49F040 etc) in PLCC-32
		    socket
		- Boot EPROM:  128Kx8bit, 256Kx8,  512Kx8, 1024x8, in DIL-32 socket
	On-board peripheral chips:
		- Programmable logic: 2x Altera EPM7128AETC100-10,  use free MAX+PLUS II
					BASELINE Software to reprogram it ( http:// 
					www.altera.com/ products/software/pld/products/
					max/sof-emax_baseline.html )
		- Analog-to-digital converters:
			Two high frequency AD9226ARS (12-bit,  60MSPS), 8 diff channels
			multiplexed into each.
			Low frequency 8 multiplexed channels into one ADC7818 (12-bit , 0.5MSPS)
		- Digital-to-analog converter:
			MAX5742EUB (4 channels, 12bit, 1MSPS)
Benchmarking:
FFT example (real FFT with bit reversal, see RFFTrad2.asm) coded in assembly using
pipelined instructions.  
FFT length	Exec Time ms  (at 60MHz clock)	
64			0.021	
128			0.039	
256			0.079	
512			0.166	
1024			0.358	
2048			0.772	
4096			1.67	
8192			3.60	

I/O interfaces and connectors:

J1 - “DIGITAL“ , DIL header, 40 pins, pitch 0.100” (2.54mm)
Pins 1,3,5,7,9,11,13,15,17,19,21,23,37 - TTL/LVC-CMOS inputs, 3V logic, 5V tolerant
					(all except pin 15, can be re-programmed as outputs 						through Altera PLD)
Pins 25,27,29,31,33,35 - bi-directional high speed (60MHz) synchronous serial port interface
                                        (signals RFS,RCLK,DR,TFS,TCLK,DT respectively)
Pin 39 - optionally connected to +5V or +3.3V supply (default=not connected)
Pins,2,4,6,8,… - GND (all even pins)
Note: all I/O pins (except 15,25,27,29,31,33,35) are re-programmable by U52 PLD (Altera EPM7128)

J2 - “ANALOG” , DIL header, 40 pins, pitch 0.100” (2.54mm)
Pin 1,3,5,7,9 - analog in., single ended, low freq. (30Hz-0.5MHz)
                       AC coupled,  33K, 5Vpp, 
Pins 11,13 -  analog in., single ended,  low freq. (0-0.5MHz), DC coupled,
                     33K, 5Vpp
Pins 21,23 - analog in., differential, high freq. (7kHz-60MHz), AC coupled, 
                   75ohm,1Vpp
Pins 25,27 - analog in., differential, high freq. (7kHz-60MHz), AC coupled,
                   75ohm,1Vpp
Pins 29,31 - analog in., differential, high freq. (0-60MHz), DC 
                    coupled,75ohm,1Vpp
Pins 15,16 - analog out., single ended, low freq. (0-1MSPS) D/A,
                   1ohm,50mAmax,0-5V
Pins,2,4,6,8,… - GND (all even pins)
Note: Pins 21,23,25,27,29,31 interface to the high frequency A/D, while pins 1,3,5,7,9,11,13,29,31 interface to the low frequency A/D.  Signals on pins 5 and 7 interface to both.

J9 - analog signal monitoring output, SMB socket.
Single-ends and feeds back the analog input signal J2 pin 29 and 31 , 0-5V, 50ohm 

J11 - analog signal monitoring output, SMB socket.
Single-ends and feeds back the analog input signal J2 pin 5 and 7 , 0-5V, 50ohm 

J12 - analog signal monitoring output, SMB socket.
Feeds back and buffers the J2 pin 3 analog input signal, 0-5V, 50ohm impedance

J13 - analog signal monitoring output, SMB socket.
Feeds back and buffers the J2 pin 1 analog input signal, 0-5V, 50ohm impedance

J10 - “SPARE” digital I/O signals,  DIL header, 10 pins, pitch 0.100” (2.54mm)

Pins 2,4,6,8 - TTL/LVC-CMOS inputs, 3V logic, 5V tolerant
Pins 5,7,9,10 - LVC-CMOS outputs, 0-3.3V, 50mA (NOT protected against 5V!)
Pin 1 = +3.3V supply
Pin 3 = GND

J14 - “LCD”, standard 14-pin SIL header (e.g. Optrex 2x8 LCD etc), pitch 0.100” (2.54mm)
TTL/LVC-CMOS I/O, 3V logic, inputs 5V tolerant, outputs only 3V.
Pin 1 - GND
Pin 2 - +5V supply
Pin 3 - Vee supply (-3 .. +5V contrast adj., through potentiometer P3)
Pin 4 - RS (register select)
Pin 5 - R/W# (read/notwrite select)
Pin 6 - E  (enable)
Pins 7..14 - D0..7  (data bus, outputs)
Note: all I/O pins are re-programmable through U21 PLD (Altera EPM7128)

J15 - “USB I/F” parallel interface to USB daughterboard,  DIL 10 pins, pitch 0.100” (2.54mm). 
All I/O pins are TTL/LVC-CMOS, 3V logic, 5V tolerant as inputs but not as outputs.
Pin 1:  -RXF (RX Full flag input)
Pins 3,5,7,9,11,13,15,17: UD0..7 (data bus, tri-state I/O)
Pin 19:  -RD (read strobe output)
Pin 21:  -TXE (TX FIFO Empty output)
Pin 23:  -USBRST (reset output)
Pin 25:  -WR (write strobe input)
Pins 22,24: reserved 
Pin 26:  +5V supply
Pins,2,4,6,8,10,12,1416,18,20:  GND 
Note: all I/O pins are re-programmable through U21 PLD (Altera EPM7128)

J16 - “DSP EMUL” JTAG DSP emulator,  DIL-10 header, pitch 0.100” (2.54mm)
TTL/LVC-CMOS inputs, 3V logic
Pin 2 - /EMU
Pin 6 - TMS
Pin 8 - TCLK
Pin 10 - /TRST
Pin 12 - TDI
Pin 14 - TDO
Pins 3,4,5,11 - not connected (pin 3 removed)
Pin 7 - pulled up to +3.3V through 20k ohm
Pin 1,9,13 - GND

J18 - “PLD” JTAG PLD prog. header for U21 and U52,  DIL-10, pitch 0.100” (2.54mm)

TTL/LVC-CMOS inputs, 3V logic  
Pin 1 - TCLK
Pin 3 - TDO
Pin 5 - TMS
Pins 6,7,8 - not connected 
Pin 9 - TDI
Pin 4 - +5V supply
Pin 2,10 - GND